The invention relates to a semiconductor device and fabrication thereof, and in particular to a memory device circuit, structure and fabrication thereof.
Dynamic random access memory (DRAM) is a semiconductor device popular for various electronic applications. Typically, a DRAM unit comprises a transistor and a capacitor, in which source electrode of the transistor is connected to a bit line, and gate electrode is connected to a word line. An opposed electrode of the capacitor is coupled to a voltage source, and a dielectric layer is interposed between a storage electrode and the opposed electrode. As known in the art, the transistor acts as a switch for controlling reading and writing data. Word 1 or 0 is presented according storage of electrons in the capacitor to store electronic information.
FIG. 1 is a top view of conventional semiconductor device 10. FIG. 2 is a cross-section along line A-A′ of FIG. 1. Referring to FIG. 1 and FIG. 2, a semiconductor device 10 is disposed on a substrate, comprising a plurality of word lines 12 along a first direction 30, and a plurality of bit lines (not shown) along a second direction 40. As mentioned above, word lines 12 can act as a gate, and a doped region in an active area 20 can act as a source 24 and a drain 25, in which a MOS transistor comprises the source 24, drain 25 and gate.
In addition, a plurality of deep trenches (DT) 14 is disposed in the semiconductor substrate, comprising a capacitor 18 at the bottom thereof. The deep trenches 14 further comprise buried straps 23 on the one side of the sidewalls and adjacent to the buried conductive layers 22, and isolation structures 28 on another side to avoid shorts between the capacitor 18 and the word line 12b. Thus, the capacitors 18 can be coupled to the word lines 12b (MOS transistors) through the buried straps 23.
As shown in FIG. 1, the semiconductor memory device 10 comprises a plurality of memory units 50, each comprising a capacitor 18 at a lower portion of the deep trench 14 and a transistor 26 nearby. Two adjacent memory units 50 use two adjacent source electrodes 24. Thus, memory units 50 can be written to and erased when voltage is applied to the bit line and word line 12.
The distance between two adjacent memory units will be reduced with shrinkage of the semiconductor device, and device density will be increased at the same time. As shown in FIG. 1, in a conventional semiconductor memory device, the shortest distance L1 between two adjacent memory units 50 is a distance between the deep trench 14 and the active area 20 of the memory unit 50. In a semiconductor memory device 10, it is likely to induce device failure when L1 is too small. Consequently, a wide enough distance is required to avoid such device failure. To get a wide enough distance, the size of the deep trench 14 must be reduced to increase L1. Data storage time and process window, however, are affected when the memory 50 unit size is decreased.